1. Field of the Invention
The present invention relates to a method of selective metallization in a semiconductor apparatus such as a semiconductor integrated circuit apparatus (referred to as “IC” hereinafter) as well as in a display apparatus such as a liquid display apparatus (referred as to “LCD” hereinafter) having a logic circuit, a scanning circuit, a switching circuit for pixels, and so forth, a method of selective metallization, a substrate apparatus and a method of forming a metallic wiring layer, more particularly, to a method of forming a metallic wiring layer in the region selected on a substrate including a basic substrate such as a semiconductor substrate, a glass substrate, a plastic substrate, and so forth and one or more layers or thin films as stacked on those substrates, a method of forming a metallic wiring layer, a method of selective metallization, an apparatus for selective metallization and a substrate apparatus.
2. Description of Prior Art
In the manufacture of an IC, especially, a large scale integrated circuit apparatus (LSI) and an ultra large scale integrated circuit apparatus (ULSI), a circuit wiring material having a lower resistivity is required in order to obtain the high speed signal transmission in circuits for the purpose of the realization of the high density integration of devices and the high speed operation. Similarly, in the manufacture of a LCD, a circuit wiring material having a lower resistivity is also required in order to meet a demand for increase of the wiring length for a large screen, miniaturization of each semiconductor device for increasing the number of pixels per unit area, installation of a lot of peripheral circuits on a main substrate, monolithic integration with a memory function, and so forth.
Aluminum (Al) having been generally used as the wiring material has a resistivity of about 5 μΩcm and can be formed into a fine pattern. However, if a fine Al wiring pattern is placed under the conditions where there exist the high temperature as well as the high stress, electron transfer and stress take place in the Al wiring pattern and as a result, some of fine Al wires comes to be broken due to migration caused by the above electron transfer and stress. Besides, even if aluminum has such a resistivity as mentioned above, it would set a limit to further improvement of the high speed signal transmission as mentioned above.
Thus, copper (Cu) having a resistivity of about 2 μΩcm and some alloys thereof are watched with interest as a material having a lower resistivity than aluminum. A Cu wiring pattern having the same film thickness as an Al wiring pattern has a lower electric resistance than the Al wiring pattern. Besides, the anti-migration character of the Cu wiring pattern is superior to that of the Al wiring pattern.
As one of methods of forming a Cu wiring pattern using copper as a wiring material, there is known a combination method combining a conventional film forming method and a reactive ion etching (referred to as “RIE” hereinafter) method (referred to as “film forming and etching method” hereinafter). According to this method, a thin copper film is first formed on a substrate or a layer-stacked plate so as to cover the almost all the surface of it and then, the thin copper film formed in a region except the one formed in a region reserved for a predetermined Cu wiring pattern is removed by the aforesaid etching method.
A damascene method is another known method of forming the Cu wiring pattern (e.g., refer to JP Patent Public Disclosure No. 11-135504). According to this method, a groove for wiring use (referred to as “wiring groove” hereinafter) is first formed in an insulating film formed on the surface of the substrate or the layer-stacked plate such that the wiring groove has the same pattern as an objective Cu wiring pattern. Then, a thin copper film is formed within the wiring groove as well as on the surface of the insulating film by means of a sputtering method such as a physical vapor deposition (PVD) method, or of a plating method, or of a chemical vapor deposition (CVD) method using an organometallic material, such that Cu film is formed inside the wiring groove or on the insulating film to fill it adequately. Then, the copper thin film except the one buried in the wiring groove is removed by chemical mechanical polishing method or etch back method, thereby a buried type Cu wiring pattern being formed.
As still another method of forming a Cu wiring pattern, there is known a method wherein there are provided on a substrate or a layer-stacked plate two regions made of two kinds of materials of which conductivities are different from each other and then, a copper thin film is formed only in the conductive region by means of the CVD method (referred to as “conductivity CVD method” hereinafter) (e.g., see the Patent Document 1 as indicated below). According to this method, prior to the selective formation of the copper thin film, in order to form a conductive region, a conductive film is first formed on the substrate or the layer-stacked plate and then, the copper thin film formed in the region other than the aforesaid region is removed by etching. After this, Cu is deposited only on the conductive film formed on the aforesaid region by means of the CVD method.
In the film forming and etching method and the damascene method as described in the above, the copper thin film once formed on almost all the surface of the substrate or the layer-stacked plate is removed except that which is formed in the region constituting the Cu wiring pattern. This not only decreases the Cu use efficiency but also invites a raise in the product cost. Besides, in the conductivity CVD method as described in the above, as the conductive film pattern formation necessary for forming the copper thin film is carried out by means of the conventional film forming method as well as the conventional etching method, the region of the conductive film to be removed becomes larger, which comes to lower the use efficiency of the conductive film material.
In order to obviate the decrement issue in the material use efficiency caused by the method of etching and polishing the conductive film as mentioned above, there has been proposed a photo-chemical reaction method so far (e.g., see the Patent Document 2 as indicated below). This photo-chemical reaction method makes use of decomposition of an organometallic substance by mean of light irradiation to directly form the copper thin film in the form of a wiring pattern on the substrate or the layer-stacked plate.
In this method, first of all, the substrate or the layer-stacked plate (referred to as “a plate to be treated” hereinafter) is placed in a gas of an organometallic raw material and then, a desired region on the plate to be treated is selectively irradiated by a light such as laser beam. The organometallic raw material receiving the light irradiation is photo-decomposed, so that nuclei made up of the metal of the same kind as caused by the photo-decomposition is formed on the surface of the above selected region of the plate to be treated. Then, a metallic film is formed on the above metallic nuclei by means of the CVD method or the electroless plating method. In the time of forming the metallic film, the metal deposition starts from respective metal nuclei and then, the metallic film is formed on the metal nuclei.
Patent Document 1: JP Patent Laid-Open Publn. No. 2-256238.
Patent Document 2: JP Patent Laid-Open Publn. No. 2000-91269 (pp. 4 to 5, FIG. 6).
However, the above photo-chemical reaction method includes the following problem. FIGS. 12(a) and 12(b) of the accompanying drawings are diagrams schematically showing a method of forming a metallic wiring layer by means of the aforesaid photo-chemical reaction method. Now, the process of forming metallic nuclei 804 and a metallic film 808 in a predetermined selected region on a substrate 801 will be explained with reference to FIGS. 12(a) and 12(b). As shown in FIG. 12(a), the organometallic material molecules 802 in the gas atmosphere, which become sources for forming metallic nuclei 804, are introduced into a film deposition chamber and at the same time, the light irradiation 806 is carried out against the surface of the substrate 801 through a mask 807, thereby the photo-decomposition reaction of the organometallic raw material molecules 802 taking place in the gas phase. At this time, metallic atoms 803 caused by the photo-decomposition reaction in the gas phase in the vicinity of the surface of the substrate 801 come to adhere to the surface of the substrate 801 and form metallic nuclei 804 in the selectively light-irradiated region on the substrate 801. However, as the unnecessary metallic atoms 803 also caused by the photo-decomposition of the organometallic raw material molecules 802 in the gas phase consisting thereof are moved within the reaction chamber according to the flow of the gas of the organometallic raw material molecules 802, the metallic atoms 803 do not always adhere to the predetermined selected region on the substrate 801 but come to adhere to the region other than the above selected region, thereby unnecessary metallic nuclei 805 being formed on unselected regions.
As described above, if the metallic film deposition is continuously carried out to the substrate 801 of which the surface includes unnecessary metallic nuclei 805 adhered thereto in unselected surface areas as well as metallic nuclei 804 adhered thereto in selected surface areas by means of the selective CVD method or the electroless plating, as shown in FIG. 12(b), the metallic film 808 grows up on the metallic nuclei 804 in the region selectively defined by the light irradiation 806 and at the same, the metallic film 809 grows up also on the metallic nuclei 805 adhered to the unselected region. As a result, the metallic film 809 comes to be deposited on unnecessary region, and the more fine the wiring pattern becomes, the more the short circuit is caused between wirings with ease. The short circuit in the wiring results in the production of defective semiconductor devices and unacceptable liquid crystal displays.